Liwa / Insights / TSMC, CoWoS & HBM

TSMC, CoWoS & HBM: the real bottleneck behind the GPU shortage

Liwa Insights·15 May 2026·8 min read

Ask why GPUs are scarce and most people say "everyone wants them." True, but incomplete. The deeper answer lives in a step of manufacturing almost nobody outside the industry can name, and once you see it, the whole shortage rearranges itself in your head.

The shortage has three doors, not one

The AI silicon bottleneck isn't a single wall. It's a three-way constraint: advanced logic (2nm/3nm), CoWoS advanced packaging, and HBM memory. And among the three, packaging is the binding one, TSMC's advanced-packaging backend fabs are reported fully booked with 52-78 week lead times (Fusion Worldwide, Silicon Analysts).

CoWoS, "chip-on-wafer-on-substrate", is how you bolt a giant GPU die to its stacks of HBM on one package. No CoWoS, no modern accelerator. And demand for it is exploding: TSMC sees AI wafer demand rising ~11× from 2022 to 2026, with CoWoS capacity growing at a >80% CAGR across 2022-27 (TrendForce).

52-78 wksCoWoS packaging lead time
>50%Of 2026-27 CoWoS reserved by NVIDIA
~11×AI wafer demand growth, 2022→2026

NVIDIA already bought the scarce thing

Here's the move that tells you who understands the constraint: NVIDIA reportedly reserved more than half of TSMC's CoWoS capacity for 2026-27 (DigiTimes). When the gate is packaging, you don't fight for chips, you buy the packaging line. Meanwhile TSMC races to expand: 2nm and A16 capacity growing at a ~70% CAGR for 2026-28, Arizona output rising ~1.8× year-over-year in 2026, and a CoWoS roadmap reaching 20 HBM stacks by 2028 and 24 by 2029 (Electronics Weekly, TechSoda, Tom's Hardware).

If the smartest buyer in the market secured the upstream bottleneck years in advance, what's the equivalent move for everyone downstream, and which input have you not locked in yet?

Follow the scarcity downstream

Trace the chain. Logic fab → packaging → HBM → finished GPU → rack → a powered, cooled place to run it. Capacity is being added at every upstream step, but it takes years and the leading buyer has first claim. So the silicon will keep arriving in a steady, rationed trickle through 2027, not a flood.

Now ask the operator's question: if chips are rationed for years, what becomes the gating factor for actually deploying compute? Not the GPU, that's someone else's queue. It's whether you have somewhere dense, cheap and cool to plug it in the moment your allocation clears. The scarcity doesn't disappear at the end of the chain. It just changes form.

Where this meets Liwa

You can't buy your way to the front of TSMC's CoWoS queue, but you can lock in the downstream input nobody's rationing yet: powered, liquid-cooled space at a fixed price. Liwa pre-sells 150 kW racks at $0.10/kWh on a founder rate held for 36 months. When your rationed silicon finally ships, the room is already yours, and the power price is already fixed.

Questions we're sitting with

Silicon is rationed. Space and power don't have to be.

Lock a 150 kW-ready rack at $0.10/kWh now, so the room is ready when your GPUs clear the queue.

Sources

  1. Fusion Worldwide, Inside the AI bottleneck: CoWoS, HBM, 2-3nm
  2. Silicon Analysts, Foundry allocation status Q1 2026
  3. TrendForce, TSMC AI wafer demand & CoWoS roadmap
  4. DigiTimes, NVIDIA books over half of CoWoS for 2026-27
  5. Electronics Weekly, 2nm/A16 capacity 70% CAGR
  6. Tom's Hardware, TSMC next-gen CoWoS roadmap

Lead times, bookings and capacity figures are industry reporting/estimates as of May 2026.